1. Field of the Invention
The invention relates generally to printed circuit board testing, and more particularly to identifying open and shorted connections to components on a printed circuit board.
2. Description of Related Art
Detecting open solder connections to components such as integrated circuit devices, connectors, and sockets on printed circuit board (PCB) assemblies continues to be a major challenge on today's manufacturing floor. Many PCBs are designed for testing by connecting test pads to signal transmission paths on the board. These test pads provide electrical contact points for test equipment.
However, connecting a test pad to signal path may undesirably change the electrical characteristics of the signal path, particularly, if the signal path caries high speed signals. FIG. 1A illustrates an example of a transmission path to which a test pad 110 has been connected for use as a testing contact point. In this example the transmission path forms a microstrip line 100 connecting a device 101 to a device 103.
FIG. 1B illustrates a simple transmission line model representing the electrical characteristics of the microstrip 100 with a test pad 110. The test pad 110 increases the capacitance of the microstrip in this region, resulting in a substantial decrease in the impedance of the signal path near the test pad 110. That is, the impedance, Z1, at the test pad 110 may be substantially less than the impedance, Z2, elsewhere along the microstrip line (i.e., Z1<Z2).
For high speed signals, such changes in impedance can cause reflections or other undesirable effects that interfere with reliable signal transmission. Thus, test pads may limit the signaling speed that may be reliably achieved on a transmission path.
Some contemporary techniques that do not require test pads rely on onboard boundary scan devices to generate square wave test signals on the transmission paths. Other integrated circuit devices, connectors and sockets connected to the transmission path will receive the signal which is then capacitively coupled to a nearby detector plate.
Commercial applications of this opens test technologies rely upon applying a periodic signal in a narrow range of frequencies for performing opens measurements. The test frequency is typically near 10 KHz because lower frequencies generally result in lower detected signal amplitude, which will lower fault coverage. Frequencies in excess of 10 KHz tend to couple into the detector plate from the PCB rather that the component being tested, resulting in false passes.
This narrow range of useable frequencies becomes problematic when the stimulus is being synthesized through a boundary scan chain. This is because the square wave output frequency on a boundary scan output pin is a function of the test access port (TAP) test clock (TCK) frequency as well as the number of scan cells that are in the scan chain. As a result, with the vast variety of board types with varying boundary scan integrated circuit (IC) content and different number of scan cells, it is difficult for suppliers to provide a stimulus frequency that is within the range of their hardware operating envelope.
Some automatic test equipment (ATE) suppliers have promoted new boundary scan commands inside the IC silicon design to make testing simpler. One such command is called Extest_Toggle. When this command is used, a selected output pin will toggle at exactly one half the TCK input clock frequency, thus eliminating the interdependence between the output pin's clock frequency and the scan chain length. However, this new boundary scan command has not been widely implemented in semiconductor devices typically mounted to PCBs.